- Copy
- Cut
- Paste
- Delete
- Undo
- New Circuit
- Insert Subcircuit
- Center Focus
Circuit Elements
null
Layout Elements
Timing Diagram
Testbench
// Write Some Verilog Code Here!Verilog Module
This is an experimental module. The code is not saved unless the "Save Code" button is clicked.
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Properties
PROJECT PROPERTIES
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Circuit:
Clock Time (ms):
Clock Enabled:
Lite Mode: